1. Field of the Invention
The present invention relates to a semiconductor storage device such as NAND-type EEPROM and particularly to an improvement of an interface for processing control signals, adapted to control a memory core including a memory cell array, a command, address and data.
2. Description of the Related Art
FIGS. 1A to 1F are views illustrating input waveforms during a write operation to an ordinary NAND-type flash memory having an asynchronous interface.
FIG. 1A illustrates a chip enable signal CEB (negative logic). FIG. 1B illustrates a write enable signal WEB (negative logic). FIG. 1C illustrates a command latch enable signal CLE (positive logic). FIG. 1D illustrates an address latch enable signal ALE (positive logic). FIG. 1E illustrates a read enable signal REB (negative logic). FIG. 1F illustrates an I/O status.
In the example illustrated in FIGS. 1A to 1F, the chip enable signal CEB (negative logic) is pulled down to low level to select the chip.
In cycle 1, the write enable signal WEB (negative logic), adapted to select input operation, is pulled down to low level. Further, the command latch enable signal CLE (positive logic), adapted to select command input, is pulled up to high level. Still further, the address latch enable signal ALE (positive logic), adapted to select address input, is pulled down to low level.
When the write enable signal WEB switches from low level back to high level, the chip loads, as a command, a code input from I/O adapted to input a command or address, and adapted to input and output data.
In cycle 2, the command latch enable signal CLE is pulled down to low level. Further, the address latch enable signal ALE is pulled up to high level. As a result, when the write enable signal WEB switches from low level back to high level, the chip loads a code input from the I/O as an address. In this example, cycles 2 to 6 are address inputs.
In cycle 7, the command latch enable signal CLE is pulled down to low level. Further, the address latch enable signal ALE is pulled down to low level. As a result, the chip loads a code input from the I/O as data.
In cycle n, the command latch enable signal CLE is pulled up to high level. Further, the address latch enable signal ALE is pulled down to low level. As a result, the chip loads a code input from the I/O as a command. This initiates the write process in the chip.
In this example, the read enable signal REB (negative logic), adapted to select output operation, remains at high level, which keeps the signal REB inactive.
FIG. 2 is a block diagram illustrating a configuration example of an ordinary NAND-type flash memory having an asynchronous interface which can implement the example in FIG. 1.
A NAND-type flash memory 1 in FIG. 2 includes an interface circuit 2, a command decoder/command latch 3, a low address latch 4, a column address latch 5, a control logic circuit 6, a page buffer 7 and a memory core 8 which includes a memory cell array having NAND-type memory cells arranged in an array form.
The interface circuit 2 includes input buffers 21 to 26, an output buffer 27 and terminals T21 to T26.
The terminal T21 is an input terminal (pin) for the write enable signal WEB. The terminal T22 is an input terminal (pin) for the address latch enable signal ALE. The terminal T23 is an input terminal (pin) for the command latch enable signal CLE. The terminal T24 is an input terminal (pin) for the read enable signal REB. The terminal T25 is a data I/O terminal (input/output pin). The terminal T26 is an input terminal (pin) for the chip enable signal CEB.
In FIG. 2, the input terminal T26 for the chip enable signal CEB is connected to the input buffer 26. The input buffer 26 is typically active.
As the chip enable signal CEB, which is a chip select signal, goes low, the input buffers 21 and 24 change from inactive to active status. The input buffer 21 is connected to the terminal T21 for the write enable signal WEB, and the input buffer 24 to the terminal T24 for the read enable signal REB.
In the example of FIG. 1, as the write enable signal WEB, which is an input select signal, goes low next, the input buffers 23, 22 and 25 change from inactive to active status. The input buffer 23 is connected to the terminal T23 for the command latch enable signal CLE. The input buffer 22 is connected to the terminal T22 for the address latch enable signal ALE. The input buffer 25 is connected to the data input/output (I/O) terminal T25.
On the other hand, the read enable signal REB fed to the terminal T24 remains at high level. As a result, the output buffer 27 connected to the I/O remains inactive.
As the input buffers 23 and 22 are activated, the command latch enable signal CLE, the address latch enable signal ALE and the code from the I/O terminal T25 are input and decoded by the command decoder 3. The code is accepted at the leading edge of the write enable signal WEB. If the code is a command, it is loaded into the command latch 3. If the code is an address, it is loaded into the address latch 4 or 5. On the other hand, if the code is data, it is transferred to the page buffer 7.
An ordinary NAND-type flash memory having an asynchronous interface is relatively slow in operation. Thus, the above operation is completed within a cycle.
Incidentally, NAND-type flash memories have peripheral circuitry transistors constructed in the same manner as their memory cell. Peripheral transistors are fabricated simultaneously when the memory cell is formed, thus keeping down the costs.
FIG. 3 illustrates a sectional view of peripheral transistors. These transistors differ from the memory cell in that a floating gate FG and a control gate CG are connected together via a contact CNT.
Therefore, the gate oxide film thickness of peripheral transistors is determined by the memory cell film thickness. Further, the gate oxide film thickness of the memory cell is physically determined by the retention characteristics of the memory cell and limited to about 8 to 9 nm. For this reason, the gate oxide film thickness of peripheral transistors is also limited to 8 to 9 nm despite advancement of the process generations.